1. Field of the Invention
The present invention relates generally to a semiconductor integrated circuit device and a storage device. More specifically, the invention relates to the semiconductor integrated circuit device and the storage device for raising a power supply voltage supplied from the outside to drive a semiconductor circuit, such as a flash memory, which is capable of batch erasing stored data.
2. Description of the Background Art
A flash memory, which is a kind of a non-volatile semiconductor memory, comprises a matrix arrangement of electrically erasable programmable read-only memory (EEPROM) cells, which are capable of electrically writing and erasing data.
FIG. 25 is a diagram illustrating the structure of a non-volatile semiconductor memory of this type. Each of memory cells in a semiconductor chip comprises a stack gate type transistor having a floating gate FG and a control gate CG. When electrons are injected into the floating gate FG or when electrons are emitted from the floating gate FG, a threshold voltage varies. By utilizing this variation in threshold voltage, data are written in and read out of the respective memory cells.
Specifically, logic "1" or "0" is determined by whether or not the current flows when the power supply voltage is applied to the control gate CG of a memory cell to be read out. The threshold voltage of a memory cell is about 2 V when the memory cell has logic "1" and higher than or equal to 5 V when it has logic "0".
In a conventional flash memory, since both of a power supply voltage supplied from the outside and a control gate voltage during readout are set to 5 V, there is particularly no problem even if the power supply voltage is applied directly to a control gate CG during readout.
In recent years, with the miniaturization of memory cells and the increase of memory capacity, it is required to lower the power supply voltage supplied from the outside; therefore, the external power supply voltage has generally been set to 3 V.
When the power supply voltage is set to 5 V as the prior art, the difference between the voltage VG applied to the control gate CG during readout and the threshold voltage Vth when the memory cell has logic "1" is VG-Vth=5-2=3 V. On the other hand, when the power supply voltage is 3 V, VG-Vth=3-2=1 V, which is a third of that when the power supply voltage is 5 V, so that the current flowing through the memory cell (which will be hereinafter referred to as a "cell current") is decreased. The decrease of the cell current decreases the readout rate, and also decreases the margin of fluctuation in the power supply voltage.
Consequently, there is proposed a technique for raising the power supply voltage, which is supplied from the outside (which will be hereinafter referred to as an "external power supply voltage Vccext") in a semiconductor chip, to higher voltage than 3 V, to generate an internal voltage Vccint, and for applying the internal voltage Vccint to the control gate of the memory cell. This internal voltage Vccint must be set to 5 V even in a stand-by state, in which data are not written in and read out of the memory cell. Because if the internal voltage Vccint is set to be lower than 5 V during the stand-by state, the voltage level of the internal voltage Vccint must be started to rise immediately after the operation state is switched from the stand-by state to a memory access state. Therefore, it takes a lot of time until the internal voltage Vccint reaches 5 V, so that it is not possible to read data out of the memory cell during that period of time.
Accordingly, the voltage level of the internal voltage Vccint in the stand-by state must be set to the same as that in the memory access state. In addition, since a non-volatile memory, such as a flash memory, is often used for a portable apparatus driven by a electric battery, the power consumption during the stand-by state is preferably as low as possible.